A low complexity digital VLSI architecture for the computation of an algebraic\r\ninteger (AI) based 8-point Arai DCT algorithm is proposed. AI encoding schemes for\r\nexact representation of the Arai DCT transform based on a particularly sparse 2-D AI\r\nrepresentation is reviewed, leading to the proposed novel architecture based on a new final\r\nreconstruction step (FRS) having lower complexity and higher accuracy compared to the\r\nstate-of-the-art. This FRS is based on an optimization derived from expansion factors that\r\nleads to small integer constant-coefficient multiplications, which are realized with common\r\nsub-expression elimination (CSE) and Booth encoding. The reference circuit [1] as well\r\nas the proposed architectures for two expansion factors a�= 4.5958 and a = 167.2309\r\nare implemented. The proposed circuits show 150% and 300% improvements in the\r\nnumber of DCT coefficients having error =0.1% compared to [1]. The three designs were\r\nrealized using both 40 nm CMOS Xilinx Virtex-6 FPGAs and synthesized using 65 nm\r\nCMOS general purpose standard cells from TSMC. Post synthesis timing analysis of 65 nm\r\nCMOS realizations at 900 mV for all three designs of the 8-point DCT core for 8-bit inputsshow potential real-time operation at 2.083 GHz clock frequency leading to a combined\r\nthroughput of 2.083 billion 8-point Arai DCTs per second. The expansion-factor designs\r\nshow a 43% reduction in area (A) and 29% reduction in dynamic power (PD) for FPGA\r\nrealizations. An 11% reduction in area is observed for the ASIC design for a�= 4.5958\r\nfor an 8% reduction in total power (PT ). Our second ASIC design having a = 167.2309\r\nshows marginal improvements in area and power compared to our reference design but at\r\nsignificantly better accuracy
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